1. Technical Field
The present invention generally relates to a semiconductor device and methods for manufacturing the semiconductor device and, more particularly, to a field effect transistor having elevated source and drain regions and methods for manufacturing the same.
2. Description of the Related Art
The semiconductor industry is increasingly characterized by a growing trend toward fabricating larger and more complex circuits on a given semiconductor chip. This is being achieved by reducing the size of individual devices within the circuits and spacing the devices closer together. The reduction of the size of individual devices and the closer spacing brings about improved electrical performance.
As the physical dimensions of field effect devices are scaled down, the operating voltages are being scaled down accordingly in order not to have excessive internal electric fields. At low operating voltages, it is increasingly important to have small parasitic resistances at the source, drain and gate regions. This is usually achieved by forming a metal silicide in these regions and making contacts to the low resistivity metal silicide.
However, in field effect devices with very shallow junctions or in fully depleted semiconductor-on-insulator SOI devices, the silicon layer at the source and drains regions are insufficient for metal silicide formation. A previous method of addressing this problem has been to thicken the source and drain by epitaxial growth of semiconductor material. However, thickening by epitaxial growth involves high-temperature processes that may cause undesirable redistribution of dopants.
A method of making a semiconductor device includes thickening source and drain regions. After a field effect device having a source region, a drain region, and a gate, is formed, a layer of semiconductor material is deposited on the device by a directional deposition method, such as collimated sputtering. Then the semiconductor material is selectively removed from side walls on either side of the gate, such as by isotropic back etching, leaving thickened semiconductor material in the source and drain regions, and on the gate.
According to an aspect of the invention, a method of thickening a source and drain of a transistor device includes directionally depositing semiconductor material, and isotropically etching the semiconductor material.
According to another aspect of the invention, a method of making a semiconductor-on-insulator device includes the steps of forming a structure including a source region and a drain region in a surface semiconductor layer of the device, and a gate and a pair of spacers on the surface semiconductor layer, wherein the spacers on respective opposite sides of the gate, and wherein the gate is operatively coupled to the source region and the drain region; directionally depositing semiconductor material on the gate, the spacers, and on exposed portions of the source region and the drain region; and selectively removing the semiconductor material to uncover at least part of each of the spacers, the selectively removing leaving a source-side slab of the semiconductor material overlying the source, and a drain-side slab of the semiconductor material overlying the drain.
According to still another aspect of the invention, a method of making a semiconductor-on-insulator device includes the steps of a) forming a structure including a source region and a drain region in a surface semiconductor layer of the device, and a gate and a pair of spacers on the surface semiconductor layer, wherein the spacers on respective opposite sides of the gate, and wherein the gate is operatively coupled to the source region and the drain region, the forming including: i) forming a gate on the surface semiconductor layer; ii) forming a source extension and a drain extension on respective opposite sides of the gate; iii) forming the spacers on opposite sides of the gate; and iv) forming the source region and the drain region; b) directionally depositing semiconductor material on the gate, the spacers, and on exposed portions of the source region and the drain region; and c) selectively removing the semiconductor material to uncover at least part of each of the spacers, the selectively removing leaving a source-side slab of the semiconductor material overlying the source, a drain-side slab of the semiconductor material overlying the drain, and a gate slab of the semiconductor material at least partially overlying the gate.
According to a further aspect of the invention, a method of making a semiconductor-on-insulator device includes the steps of forming a structure including a source region and a drain region in a surface semiconductor layer of the device, and a gate and a pair of spacers on the surface semiconductor layer, wherein the spacers on respective opposite sides of the gate, and wherein the gate is operatively coupled to the source region and the drain region; collimated sputtering semiconductor material on the gate, the spacers, and on exposed portions of the source region and the drain region; isotropically etching the semiconductor material to uncover at least part of each of the spacers, the selectively removing leaving a source-side slab of the semiconductor material overlying the source, a drain-side slab of the semiconductor material overlying the drain, and a gate slab of the semiconductor material at least partially overlying the gate; depositing a metal layer; and annealing the device to induce formation of semiconductor-metal compound regions at intersections of the slabs and the metal layer.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.